Research on a hybrid type of memory that combines the density of DRAM with the speed of SRAM is getting a boost from CHIPS and Science Act funding. The hybrid gain cell memory research is one of the projects within the California-Pacific-Northwest AI Hardware Hub, which is receiving US $16.3 million from the U.S Department of Defense, according to a late September announcement.
This group is focused on developing more energy efficient hardware for AI—and memory is central to that goal, says Stanford University electrical engineer H.-S. Philip Wong, who chairs the hub. Moving data back and forth between logic and memory slows down GPUs and is the main driver of AI energy consumption. Having more fast, dense memory on the chip would help alleviate these constraints, but options are limited. “We want to provide better options so designers can optimize better,” whether they want speed or energy savings, says Wong.
Wong’s team is developing an alternative memory design that combines the advantages of SRAM and DRAM. DRAM can store a lot of data in a relatively small footprint, since it’s made of just one transistor and one capacitor, but reading that data is comparatively slow. SRAM can be read out more quickly, but the cells are relatively large, made up of several transistors. The Stanford team’s gain cell memory combines the small footprint of DRAM with a speed that is nearly as fast as SRAM.
Combining the Best From DRAM and SRAM
Gain cells are similar to DRAM, but use a second transistor instead of a capacitor to store data. That data is stored in the form of charge on the second transistor’s gate, which is a capacitive structure that controls the flow of current through the transistor. Capacitors in ordinary DRAM leak their charge over time, and reading out the data destroys it. In a gain cell, reading out the signal is nondestructive. In fact, the read transistor provides a signal boost to the storage transistor when it’s read out—that is, it provides gain. In DRAM, “each time you read the information, you destroy the information,” says Stanford electrical engineering PhD student Shuhan Liu. “The gain cell is better because it adds an additional read transistor. You’re not just reading the charge, you’re reading an amplified signal.”
However, gain cells have their own limitations. When both of the transistors are silicon, the data leaks relatively quickly. When they are both made of oxide semiconductors readouts are slow.
Liu and Wong overcame these limitations by combining a silicon read transistor with an indium tin oxide write transistor to make better performing, hybrid gain cell memory. The resulting device held its bit for more than 5000 seconds—ordinary DRAM must be refreshed every 64 milliseconds—and was about 50 times faster than a similar oxide-oxide gain cell. The group initially presented their results at the IEEE Symposium on VLSI Technology and Circuits in June.
The combination of silicon and oxide-based transistors “reduces the cell footprint, and also the oxide transistor has low leakage current,” says Shimeng Yu, an electrical engineer at Georgia Tech. This improves the hybrid memory’s data retention time by orders of magnitude compared to silicon-silicon gain cells, he says.
Wong says these hybrid memory cells could be integrated onto logic chips. “It’s an opportunity to rearchitect computers,” he says. These sorts of designs could change how memories are used. Moving beyond having access only to flash, DRAM, and SRAM will be “like going from a 3-gear bicycle to a 20-gear bicycle,” he says.
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